How this works. A UART divides its peripheral clock down to produce a sampling
clock, usually 16× or 8× the bit rate, then divides again by the oversampling factor. The
divisor is an integer, so most clock and baud combinations cannot be hit exactly — the error is
whatever the rounding leaves behind. What matters is not the error itself but how much it
accumulates: the receiver resynchronises on each start edge, then samples the middle of each
bit, so the worst case is the stop bit about 9.5 bit times later. Drift there must stay well
under half a bit, which is where the familiar ±2 % rule of thumb comes from. Both ends
contribute, so two devices each 2 % off in opposite directions is already 4 %.
This error is above ±2 %. It may work between two accurate endpoints and fail against a device with its own error in the opposite direction — pick a clock that divides more cleanly if you can.